Nibble Mode DRAM




<storage> A standard DRAM where four successive bits can be clocked out of the single data line by successive pulses on the CAS\ line while RAS\ is active.

A column address is only required for the first bit.

This mode is now unfashionable but can be found on some older 64 kilobit and 256 kilobit chips.



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NIAL
NIAL Systems Ltd.
NIAM
nibble
dynamic random access memory
Synchronous Dynamic Random Access Memory
NIC
NIC.DDN.MIL
NICE
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