Pipeline Burst Cache




<hardware, storage> (PB Cache) A synchronous cache built from pipelined SRAM.

A cache in which reading or writing a new location takes multiple cycles but subsequent locations can be accessed in a single cycle.

On Pentium systems in 1996, pipeline burst caches are frequently used as secondary caches.

The first 8 bytes of data are transferred in 3 CPU cycles, and the next 3 8-byte pieces of data are transferred in one cycle each.



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pin-out
PIP
pipe
pipeline
pipeline break
 PB Cache
Pipeline Burst Cache
Pipelined Burst Cache
 pipelined
Pipelined Burst Cache
pipeline stall
pipelining
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