RFC 1152 (rfc1152) - Page 2 of 23

Workshop report: Internet research steering group workshop on very-high-speed networks

RFC 1152                  IRSG Workshop Report                April 1990


   implementation to complete relayering of function.  Clark asserted
   that currently even the basic problem to be solved is not clear, let
   alone the proper approach to the solution.

   Mats Bjorkman (Uppsala University) described a project that involved
   the use of an outboard protocol processor to support high-speed
   operation.  He asserted that his approach would permit accelerated
   processing of steady-state sequences of packets.  Van Jacobson (LBL)
   reported results that suggest that existing protocols can operate at
   high speeds without the need for outboard processors.  He also argued
   that resource reservation can be integrated into a connectionless
   protocol such as IP without losing the essence of the connectionless
   architecture.  This is in contrast to a more commonly held belief
   that full connection setup will be necessary in order to support
   resource reservation.  Jacobson said that he has an experimental IP
   gateway that supports resource reservation for specific packet
   sequences today.

   Dave Borman (Cray Research) described high-speed execution of TCP on
   a Cray, where the overhead is most probably the system and I/O
   architecture rather than the protocol.  He believes that protocols
   such as TCP would be suitable for high-speed operation if the windows
   and sequence spaces were large enough. He reported that the current
   speed of a TCP transfer between the processors of a Cray Y-MP was
   over 500 Mbps.  Jon Crowcroft (University College London) described
   the current network projects at UCL.  He offered a speculation that
   congestion could be managed in very high-speed networks by returning
   to the sender any packets for which transmission capacity was not
   available.

   Dave Feldmeier (Bellcore) reported on the Bellcore participation in
   the Aurora project, a joint experiment of Bellcore, IBM, MIT, and
   UPenn, which has the goal of installing and evaluating two sorts of
   switches at gigabit speeds between those four sites.  Bellcore is
   interested in switch and protocol design, and Feldmeier and his group
   are designing and implementing a 1 Gbps transport protocol and
   network interface.  The protocol processor will have special support
   for such things as forward error correction to deal with ATM cell
   loss in VLSI; a new FEC code and chip design have been developed to
   run at 1 Gbps.

   Because of the large number of speakers, there was no general
   discussion after this session.








Partridge